This application claims the benefit of Korean Patent Application No. 2001-81562, filed on Dec. 20, 2001, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display panel of line on glass (LOG) type and a fabricating method thereof that is adaptive for minimizing line resistance of LOG-type patterns provided on the liquid crystal display panel.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type, and a driving circuit for driving the liquid crystal display panel.
In the conventional liquid crystal display panel, gate lines and data lines are arranged in such a manner to cross each other. The liquid crystal cell is positioned at each area where the gate lines cross the data lines. The liquid crystal display panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each pixel electrode is connected, via the source and drain electrodes of a thin film transistor acting as a switching device, to any one of data lines. The gate electrode of the thin film transistor is connected to any one of the gate lines allowing a pixel voltage signal to be applied to the pixel electrodes for each one line.
The driving circuit includes a gate driver for driving the gate lines, a data driver for driving the data lines, a timing controller for controlling the gate driver and the data driver, and a power supply for supplying various driving voltages used in the LCD. The timing controller controls a driving timing of the gate driver and the data driver and applies a pixel data signal to the data driver. The power supply, using input power, generates driving voltages such as a common voltage Vcom, a gate high voltage Vgh and a gate low voltage Vgl, etc, which are needed in the liquid crystal display. The gate driver sequentially applies a scanning signal to the gate lines to sequentially drive the liquid crystal cells on the liquid crystal display panel one line by one line. The data driver applies a pixel voltage signal to each of the data lines whenever the scanning signal is applied to any one of the gate lines. Accordingly, the LCD controls the light transmittance by an electric field applied between the pixel electrode and the common electrode in accordance with the pixel voltage signal for each liquid crystal cell, to thereby display a picture.
The data driver and the gate driver are directly connected to the liquid crystal display panel and integrated into a plurality of integrated circuits (ICs). Each of the data drive IC and the gate drive IC are mounted in a tape carrier package (TCP) for connection to the liquid crystal display panel by a tape automated bonding (TAB) system, or mounted directly onto the liquid crystal display panel by a chip on glass (COG) system. The printed circuit board includes a data PCB and a gate PCB.
The drive ICs are connected, via the TCP, to the liquid crystal display panel by the TAB system and receive control signals and direct current voltages inputted from the exterior over signal lines formed on a printed circuit board (PCB) connected to the TCP. The drive ICs are also connected to each other. More specifically, the data drive ICs are connected, in series, via signal lines formed on the data PCB, and commonly receive control signals from the timing controller, a pixel data signal and driving voltages from the power supply. The gate drive ICs are connected, in series, via signal lines formed on the gate PCB, and commonly receive control signals from the timing controller and driving voltages from the power supply.
The drive ICs mounted onto the liquid crystal display panel by the COG system are connected to each other by a line on glass (LOG) system in which signal lines are mounted on the liquid crystal display panel, that is, on a lower glass, and receive control signals from the timing controller and driving voltages from the power supply.
Recently, even when the drive ICs are connected to the liquid crystal display panel by the TAB system, the LOG system is employed to eliminate the PCB, and permits the manufacture of a thinner liquid crystal display. Accordingly, signal lines for connection to the gate drive ICs require relatively small signal lines, are provided on the liquid crystal display panel by the LOG system and eliminate the need for the gate PCB. In other words, the gate drive ICs of TAB system are connected, in series, to each other over signal lines mounted onto the lower glass of the liquid crystal display panel, and commonly receive control signals and driving voltage signals, which are hereinafter referred to as xe2x80x9cgate driving signalsxe2x80x9d.
For example, as shown in FIG. 1, the liquid crystal display omitting the gate PCB by utilizing LOG-type signal wiring includes a liquid crystal display panel 1, a plurality of data TCPs 8 connected between the liquid crystal display panel 1 and a data PCB 12, a plurality of gate TCPs 14 connected to other side of the liquid crystal display panel 1, data drive ICs 10 mounted in the data TCPs 8, and gate drive ICs 16 mounted in the gate TCPs 14.
The liquid crystal display panel 1 includes a lower substrate 2 provided with various signal lines and a thin film transistor array, an upper substrate 4 provided with a color filter array, and a liquid crystal injected between the lower substrate 2 and the upper substrate 4. Such a liquid crystal display panel 1 is provided with a picture display area 21 that consists of liquid crystal cells provided at intersections between gate lines 20 and data lines 18 for the purpose of displaying a picture. At the outer area of the lower substrate 2 located at the outer side of the picture display area 21, data pads extended from the data lines 18 and gate pads extended from the gate lines 20 are positioned. Further, a LOG-type signal line group 26 for transferring gate driving signals applied to the gate drive IC 16 is positioned at the outer area of the lower substrate 2.
The data TCP 8 supports the data drive IC 10, and is provided with input pads 24 and output pads 25 electrically connected to the data drive IC 10. The input pads 24 of the data TCP 8 are electrically connected to the output pads of the data PCB 12 while the output pads 25 are electrically connected to the data pads on the lower substrate 2. Thus, the first data TCP 8 is also provided with a gate driving signal transmission group 22 electrically connected to the LOG-type signal line group 26 on the lower substrate 2. This gate driving signal transmission group 22 applies gate driving signals from the timing controller and the power supply, via the data PCB 12, to the LOG-type signal line group 26.
The data drive ICs 10 convert digital pixel data signals into analog pixel voltage signals to apply them to the data lines 18 on the liquid crystal display panel.
Similarly, the gate TCP 14 is mounted with a gate drive IC 16, and is provided with a gate driving signal transmission line group 28 electrically connected to the gate drive IC 16 and output pads 30. The gate driving signal transmission line group 28 is electrically connected to the LOG-type signal line group 26 on the lower substrate 2, and the output pads 30 are electrically connected to the gate pads on the lower substrate 2.
Each gate drive ICs 16 sequentially applies a scanning signal, that is, a gate high voltage signal Vgh to a gate line 20 in response to input control signals. Further, the gate drive ICs 16 applies a gate low voltage signal Vgl to the gate line 20 in the remaining interval where the gate high voltage signal Vgh is not applied.
The LOG-type signal line group 26 usually consists of signal lines for supplying direct current voltage signals such as a gate high voltage signal Vgh, a gate low voltage signal Vgl, a common voltage signal Vcom, a ground voltage signal GND and a supply voltage signal Vcc and gate control signals such as a gate start pulse GSP, a gate shift clock signal GSC and a gate enable signal GOE. As shown in FIG. 2, a LOG-type signal line group 26 is arranged, in parallel, in a small pattern within a very confined narrow space like a pad portion positioned of an outer area of a picture display part 21.
Referring to the FIG. 2 and FIG. 3, each of the LOG-type signal lines of the LOG-type signal line group 26 includes a gate metal pattern 27 formed on the lower substrate 2, and a protective electrode 36 connected to the gate metal pattern 27, via the contact hole 38 passing through a gate insulating film 32 and a protective film 34. The protective electrode 36 is positioned at a gate pad area and a data pad area contacting the data TCP 8 and the gate TCP 14. The LOG-type signal line group 26 consists of the gate metal pattern simultaneously formed with the gate lines 20. The gate metal is a metal having a relatively large conductive value of 0.046 such as AlNd.
The LOG-type signal line group 26 is formed in a small pattern within a confined area made up of the gate metal having a relatively large conductive value, as shown the FIG. 4, the LOG-type signal line group 26 has a higher resistance value Ri than the signal lines formed in a copper film on an existent gate PCB. Further, the resistance value of the LOG-type signal line group 26 is in proportion to the line length. That is, the line resistance value increases, the farther from the data PCB 12, to attenuate a gate-driving signal. As a result, gate driving signals transferred over the LOG-type signal line group 26 are distorted due to the line resistance value of signal line group 26, causing a deterioration in the quality of a picture displayed on the picture display part 21.
Furthermore, a voltage difference occurs from a gate-driving signal applied for each gate drive IC 16 due to the line resistance value of the LOG-type signal line group 26. Since the line resistance value varies according to the length of the LOG-type signal line group 26 and increases as the LOG-type signal line group 26 is further from the data PCB 12, a gate-driving signal is attenuated. Due to a difference of gate driving signals applied for each gate drive IC 16, a cross-line phenomenon occurs between horizontal line blocks connected to different gate drive ICs 16 at the picture display part 21, causing a division of the field of display.
This cross-line phenomenon between the horizontal line blocks is caused by a gate low voltage Vgl of a plurality of gate driving signals supplied at different levels for each gate drive TCP 14, since each gate drive IC 16 due to a line resistance of the LOG-type signal line group 26. A distortion of the gate low voltage Vgl in the gate driving signals supplied over the LOG-type signal line group 26 greatly affects picture quality of the picture display part 21. The gate low voltage Vgl allows a pixel voltage charged in the liquid crystal cell to be maintained until the next pixel voltage is charged. Thus, the charged pixel voltage varies when the gate low voltage Vgl is distorted.
In order to prevent an attenuation of a gate driving signal, particularly a gate low voltage caused by a line resistance of the LOG-type signal line group 26, the LOG-type signal line group 26 must have a large sectional view or a small resistivity to attenuate a resistance component. However, since an outer area of the picture display part 21 provided with the LOG-type signal line group 26 is confined, there exists a limit in enlarging a sectional area of the LOG-type signal line group 26. Also, since the LOG-type signal line group 26 is formed from a gate metal layer, there exists a limit in reducing the conductive value. Therefore, a scheme for reducing a line resistance of the LOG-type signal line group 26 arranged in a small pattern within the confined area is required.
Accordingly, the present invention is directed to liquid crystal display panel of line on glass type and method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An advantage of the present invention is to provide a LOG-type liquid crystal display panel according to one embodiment of the present invention includes a picture display part having a plurality of liquid crystal cells, each of which is arranged at each intersection area between gate lines and data lines, and line on glass type signal lines, provided at an outer area of the picture display part by a line on glass system, applying driving signals required to drive integrated circuits that driving the gate lines and the data lines, and any one signal line of the line on glass type signal lines is provided by different metal layers formed between the insulating films and connected with each other in parallel.
In the line on glass type liquid crystal display panel according to the invention, the line on glass type signal line is formed between the gate insulating films and the protective films, via the contact hole passing through the gate insulating films and the protective films, and including the gate metal layer and the transparent conductive layer connected in parallel.
In the line on glass type liquid crystal display panel according to the invention, the line on glass type signal line is formed between the gate insulating films and is provided at a gate metal layer and a source/drain metal layer connected in parallel, via the contact hole passing through the gate insulating films.
Another advantage of the present invention is to provide the line on glass type signal line having a gate metal pattern, a source/drain metal pattern formed between the gate metal pattern and the gate insulating films, a transparent conductive material pattern formed between the source/drain metal pattern and the protective film, via contact hole passing through the gate insulating, source/drain metal pattern and the protective film, and connected with the gate metal pattern and the source/drain metal pattern, in parallel.
The line on glass type signal lines provide driving signals required in the gate drive integrated circuit for driving the gate lines and a common voltage required in a common electrode of the picture display part.
Specifically, a gate low voltage signal line for supplying a gate low voltage signal to the line on glass type signal lines is provided by different metal layers formed between the insulating films and connected with each other in parallel.
The gate low voltage signal line is arranged by a gate metal pattern provided side by side with the other line on glass type signal lines, and a transparent conductive material pattern provided between the gate metal pattern, the gate insulating films and the protective films, connected in parallel via the contact hole passing through the gate insulating films and the protective films, and overlapping with the other line on glass type signal lines to create the largest area in confined area.
Alternatively, the gate low voltage signal line is arranged according to a gate metal pattern provided side by side with the other line on glass type signal lines, and a source/drain metal pattern provided between the gate metal pattern and the gate insulating films, connected in parallel via the contact hole passing through the gate insulating films, and overlapped with the other line on glass type signal lines to have the largest area in confined area.
Further, the gate low voltage signal line is arranged according to a gate metal pattern provided side by side with the other line on glass type signal lines, a source/drain metal pattern provided between the gate metal pattern and the gate insulating films, connected in parallel via the contact hole passing through the gate insulating films, and overlapping the other line on glass type signal lines to have the largest area in confined area. Additionally, the transparent conductive material pattern provided between the source/drain metal pattern and the protective films has the largest area in confined area, connected with the gate metal pattern and the source/drain metal pattern via contact hole passing through the gate insulating films, with the source/drain metal pattern and the protective films.
A method of fabricating a line on glass type liquid crystal display panel comprising the steps of forming a gate metal pattern of the line on glass type signal lines, along with the gate electrode and the gate lines of the thin film transistor, by depositing a gate metal onto a lower substrate and then patterning it. Then forming an active layer of the thin film transistor by entirely coating a gate insulating film and depositing a semiconductor material and then patterning them, and forming source/drain electrodes and data lines of the thin film transistor, by depositing a source/drain metal and then patterning the metal. Next, forming a contact hole for exposing pads of the gate lines and the data lines, the drain electrode of the thin film transistor, and pads of gate metal pattern of the line on glass type signal line after entirely coating the protective film, and forming a pixel electrode connected to the drain electrode, a protective electrode connected to the pads of the gate line and the data line, and a transparent conductive material pattern overlapping with a gate metal pattern of the line on glass type signal line and connected to the pads of the line on glass signal lines, by depositing a transparent conductive material and then patterning the transparent conductive material.
A method of fabricating a line on glass type liquid crystal display panel comprising the steps of forming a gate metal pattern of the line on glass type signal lines, with the gate electrode and the gate lines formed from the thin film transistor, by depositing a gate metal onto a lower substrate and then patterning the metal. Next, forming an active layer of the thin film transistor by entirely coating a gate insulating film and depositing a semiconductor material and then patterning the semiconductor material. Next, forming source/drain pattern overlapping with the gate metal pattern of the line on glass type signal lines with source/drain electrodes and data lines of the thin film transistor, by depositing a source/drain metal and then patterning the metal. Next, forming a contact hole for exposing pads of the gate lines and the data lines, the drain electrode of the thin film transistor, and pads of gate metal pattern of the line on glass type signal line after entirely coating the protective film, and forming a pixel electrode connected to the drain electrode, a protective electrode connected to the pads of the gate line and the data line, and a transparent conductive material pattern connected to the pads of gate metal pattern of the line on glass type signal line and the source/drain metal pattern, by depositing a transparent conductive material and then patterning the transparent conductive material.